This invention relates to semiconductor integrated delay circuits and more particularly to a semiconductor integrated delay circuit wherein the effect of semiconductor process variations and power supply voltage variations on the value of the delay are minimized.
Generally, prior art integrated delay circuits fabricated with a complimentary metal oxide semiconductor ("CMOS") process include a series of simple inverter circuits wherein the value of the delay is determined by the gate delay through one inverter and the number of inverters in the series. Such a prior art delay circuit is shown in FIG. 1. Each inverter includes a p-channel transistor and an n-channel transistor. The gates of the transistors are coupled together to form the input of the inverter and the drains of the transistors are coupled together to form the output of the inverter. The source of the p-channel transistor is connected to a source of supply voltage, designated VDD. The value of VDD is typically +5 volts for powering a CMOS circuit. The input of the first inverter in the series receives the input signal designated VIN and the output of the last inverter of the series produces the delayed output signal designated VOUT. The input signal VIN, which is a pulse or square wave, and the delayed output signal VOUT are shown in FIG. 2, where T.sub.R is the value of the rising edge delay and T.sub.F is the value of the falling edge delay.
The problem with the delay circuit of FIG. 1 is that the processing variations of the semiconductor process, which in turn affect transistor parameters, combined with the variations in the supply voltage, which varies between 4.5 volts and 5.5 volts, produces a range of delays wherein the worst case longest delay may be up to 2.5 times the worst case shortest delay. What is desired is a semiconductor integrated delay circuit wherein these effects may be minimized in order to produce a more accurate delay value.